Reborn in 2010, the AI ​​in my mind is too powerful.

Chen Yiran looked shocked, then asked with a hint of disappointment, "Are you really sure? Won't you reconsider? You're earning more money now, and the bonuses for you two will be announced at the annual meeting. Getting married now is really inappropriate. What if you get divorced later?"

My suggestion is that you shouldn't get married yet. Marriage is a grave; it's unnecessary!

Catherine looked at him with disdain: "After all that talk, you just can't bear to see our Emily get married. Let me tell you, don't even think about it, I'm going to marry Emily!"

Chen Yiran said with a straightforward expression, "How could that be? Let me tell you, many people have strange quirks, and they get more excited the more they do that. I'm not like that. I'm really trying to persuade you."

Catherine glanced at Alan Mulally, who was listening to the gossip and smacking his lips, and pulled Chen Yiran aside.

As Chen Yiran listened, his face changed color. Finally, he coughed and said, "Ahem, okay, then I'll trouble you to help me out. Are you sure you're not lying to me?"

"I'm absolutely not lying to you!"

"Okay! It's settled then!"

Chen Yiran got into the car and said to Nuno, "Drive to the dock quickly, I'm really angry right now."

Upon arriving at the Venus, Chen Yiran immediately pulled Dada, who was still sunbathing, into the bedroom and gave him a good scolding: "I told you I like fair skin, but you kept sunbathing like that."

Dada said matter-of-factly, "I don't get tanned. I'll be fair again in two days. Besides, didn't you say a while ago that tan lines were kind of cute?"

------------------Over six million words, please use your imagination-------------------------------

On December 9th, the Hawaii Convention Center in Honolulu was packed with people, and the media and analysts present were very excited.

Regardless of the specifics of today's situation, they're already prepared to give Aurora Group a little attention in their press release. After all, Aurora Group is truly amazing; holding a press conference in Hawaii is a brilliant idea, a perfect place for a publicly funded vacation.

At 2:30 p.m., Chen Yiran walked up from the right side of the backstage area. The people in the audience noticed that Chen Yiran had actually abandoned his white sweater and jeans this time, and changed into a plaid shirt and beach shorts.

Looking at the noisy discussion below the stage, Chen Yiran said with a hint of helplessness, "I know that everyone now thinks wearing a sweater to a press conference is a tradition, but this is Hawaii, and it's over 20 degrees Celsius. It's a bit much to ask me to wear a sweater."

Besides, when you're in Hawaii, you should dress in a more nautical style. I'm already doing my part to uphold our Silicon Valley tradition by sticking to my plaid shirt.

Chen Yiran ignored the applause from the audience, waved his hand, and the large screen on the stage lit up, displaying a title: Yield, determined before tape-out.

"I am very grateful to Google for entering the EDA market, which gave me a little bit of a sense of urgency, so we spent a year making another major update to our EDA suite."

Anyone who works in the chip industry knows the saying: whether a chip is usable or not is largely determined before it's even manufactured.

Traditional EDA pipelines are long, managing timing and power consumption. Yield issues mainly rely on repeated design revisions until the design is nearly perfect before tape-out. FlowEDA has significantly changed these traditional strategies.

We now have enough data, and the intervention of AI makes the combined calculation of various aspects more convenient. Today I want to propose a new concept.

Previously, everyone was familiar with Grey tube layout and Tiya tube optical correction. This year, we combined them into a closed loop called yield sensing.

Optimizing based on process fluctuations during the layout phase can also help avoid hotspots prone to defects. Virtual measurement, using data from equipment sensors to estimate the uniformity of each layer, can save a significant portion of physical measurements.

Automatic defect classification identifies defects missed by optical inspection. Process-angle modeling incorporates boundary conditions such as speed and voltage levels.

Parametric yield refers to the performance of the same design under different process deviations. Defect escape refers to defects that are not detected by optical inspection and are only exposed during the fabrication process.

All of these things we've been doing are now gradually being integrated into a whole. As long as you use our FlowEDA suite of tools, the interaction relationships between each step are calculated in advance before the chip fabrication.

In reality, there is too little actual defect data; the quantity is simply insufficient for training. This is the data we obtained by using DeepFlow to create synthetic defects and then calibrating it with a digital twin wafer fab. This is equivalent to creating a virtual production line for ourselves that never stops, allowing us to continuously correct errors.

We've been experimenting with these technologies for several months at Aurora and Samsung's wafer fabs. Our latte mocha wafers were produced using these technologies, and now the yield rate for both types of chips is approaching 90%.

After that, there was a bunch of EDA technology updates. Although the audience thought they were good, there weren't many surprises.

Since FlowEDA emerged three years ago, people have become accustomed to EDA tools named after various small animals creating all sorts of incredibly impressive results.

Moreover, what Chen Yiran talked about today is more like the synergistic effect of multiple technologies eventually merging, which is quite different from the shock of going from zero to one in the past.

However, Chen Yiran immediately announced something that excited them greatly.

"With better EDA tools, we've naturally also updated our chips. They're already widely used in Latte and Mocha. Today, I'm going to talk about the third chip launched by our Aurora Group: Caramel Macchiato!"

An exploded view was displayed on a large screen, showing a silicon interposer in the center, several small dies around it, and memory chips stacked on top of each other.

"The principle is not complicated. For a large chip, the larger the area, the worse the yield. This is a physical law of wafers. Defects are random, and the larger the area, the higher the probability of encountering them."

An 800-square-millimeter single chip might only have a 30% yield. If we break it down into four 200-square-millimeter pieces and process them separately, and then use our EDA technology, the yield of each chip will reach over 95%. After further screening using EDA strategies, the overall system yield will be incredibly high.

They are placed side by side on a silicon interposer, with densely packed micro-trace lines running through the interposer for communication between them. Then, through-silicon vias (TSVs) are used to vertically transmit the signals to the substrate. The chip and memory are placed very close together, with the distance reduced to the millimeter level, which significantly increases the bandwidth, resulting in 2.5D packaging.

Everyone knows the packaging difficulty involved. In 2.5D packaging, even a slight misalignment of the silicon interposer and TSV, a void inside, or thermal stress issues can render an entire module worth tens of thousands of dollars unusable. As a cutting-edge interconnect technology, hybrid bonding relies heavily on interface cleanliness and temperature uniformity to achieve high yields. Stress caused by differences in the thermal expansion coefficients of different materials can lead to cracking.

However, I would like to announce here that Aurora has used AI to innovate its packaging technology, from hybrid bonding to interposer wiring, and the packaging yield and thermal simulation have all passed the test. We have now successfully overcome these technical difficulties.

Finally, we made a caramel macchiato!

This chip will utilize established production lines with mature processes to manufacture each chip to the greatest extent possible.

Auxiliary dies such as I/O, power management, and analog circuits are manufactured directly on 28nm, 40nm, or even more mature production lines, while core computing dies use advanced bit-stage processes.

Finally, the newly built 2.5D advanced packaging production line of Aurora completed the processes such as silicon interposer, TSV, and hybrid bonding.

It possesses absolute advantages in five aspects: yield rate, bandwidth, heterogeneity, revitalization of aging production lines, and cost reduction in AI data centers.

At this point, the audience started to get excited. Even those who weren't experts had a basic understanding of the chip industry. Even if their understanding was insufficient, they would pretend to be excited when they saw the heated discussion around them.

Some veteran journalists have begun frantically typing away in their laptops, using simpler language to explain the meaning of caramel macchiato to their readers.

As Chen Yiran said, the yield of this chip will be very high, solving the yield problem of single large chips and breaking the memory wall of the data center, so that the chip interconnect bandwidth will no longer be limited by the PCB.

Moreover, this heterogeneous integration allows for the use of optimal processes at every stage. It can also revitalize aging production lines with mature processes, enabling many decommissioned devices to continue performing a great deal of work.

All of these factors combined will ultimately lead to a significant reduction in costs.

At the subsequent press conference, Olofson, the head of the Caramel Macchiato project team, took to the stage to explain some specific technical details of the chip.

Chen Yiran came back on stage at the end to reinforce his persona: "I want to specifically mention that I first met Olofson at the Semiconductor Show in the United States in July 2010."

At the time, he was still running Adapteva, a small company he founded, and he already had the idea of ​​using a large number of very simple cores, interconnected efficiently, to create terrifying parallel computing power.

Although the final product differs somewhat from the current one, his idea at the time was still very creative.

I have to be proud of myself, after all, I recognized his exceptional talent back then and gave him Grey, who wasn't famous yet, to use at a very low price. Although they ultimately couldn't hold on, he came to Aurora, and we still achieved some success on this route.

In contrast, when I visited TSMC's booth, the salesperson named Alex, with TSMC's usual arrogance, completely ignored me. This is a problem with companies like TSMC, and as a board member, I must make changes.

Okay, that concludes today's press conference. Oh, what's going on? Why is the power out?

While Chen Yiran delivered her lines with clumsy acting, the staff below began to frantically go on stage in the dark to make preparations.

The reporters in the audience were even more excited; there was still stock left!